Interesting papers from FPT 2011

Reconfigurable Acceleration and Dynamic Partial Self-Reconfiguration in General Purpose Computing by Ioannis Sourdis

The Realtime Image Processing Demonstration with CMA-1 : An Ultra Kazuei Hironaka, Nobuaki Ozaki and Hideharu Amano
Low-power Reconfigurable Accelerator

Cool Mega-Array: a highly energy efficient reconfigurable accelerator

OpenCL based programming for Altera FPGA

http://www.sacbee.com/2011/11/15/4055549/altera-announces-industrys-first.html
http://www.altera.com/b/opencl.html

High Speed Casio Cameras

http://www.quintic.com/hardware/highspeed_casio.htm

Hack a Canon Power Shot

Cool idea
http://www.pcmag.com/article2/0,2817,2329392,00.asp#fbid=EKAuV4xqUbB


CHDK can be found here.
http://chdk.wikia.com/wiki/CHDK

Linux on Zynq FPGA

http://www.xilinx.com/products/zynq-7000/linux.htm

AI Challenge by Google

AI Challenge by Google

Facebook Fellowship Program for PHD students

Face Fellowships

COACH

Another project to keep a look out.
Conception d’Architecture sur FPGA par Compilation et
syntH`ese

Architecture Design on FPGA by Compilation and Synthesis
https://www-soc.lip6.fr/trac/coach/export/379/anr/coach.pdf

High Level Synthesis Benchmark Suite

http://www.ertl.jp/chstone/

6th HiPEAC Workshop on Reconfigurable Computing - CALL FOR PAPERS

http://www.wikicfp.com/cfp/servlet/event.showcfp?eventid=18753&copyownerid=30648

http://www.cad.polito.it/~sterpone/WRC_2012/WRC_2012_-_Home_Page.html

Cool IDEA - Variable SMP Model from Nvidia

http://jakob.engbloms.se/archives/1496

Variable SMP –A Multi-Core CPU Architecture for Low Power and High Performance Power and High Performance
http://www.nvidia.com/content/PDF/tegra_white_papers/Variable-SMP-A-Multi-Core-CPU-Architecture-for-Low-Power-and-High-Performance_v1.1.pdf

Impact Factors

A good site to get updated impact factors.

http://www.scimagojr.com/index.php
E.g for TODAES
http://www.scimagojr.com/journalsearch.php?q=18662&tip=sid&clean=0

FASTER - FACILITATING ANALYSIS AND SYNTHESIS TECHNOLOGIES FOR EFFECTIVE RECONFIGURATION

FASTER
FACILITATING ANALYSIS AND SYNTHESIS TECHNOLOGIES FOR EFFECTIVE RECONFIGURATION
http://www.fp7-faster.eu/index.html
http://www.hpcwire.com/hpcwire/2011-10-14/maxeler_joins_eu_research_effort_to_boost_fpga_performance.html

 A project to keep a look out.

Altera joins the ARM+FPGA race :)
http://www.eetimes.com/electronics-news/4229353/Altera-integrates-ARM-processor-in-FPGAs

http://www.altera.com/devices/processor/soc-fpga/proc-soc-fpga.html

Couple of interesting webinars on HLS.

Using High-Level Synthesis and Open Source Imaging Libraries to Streamline ASIC/FPGA IP Developmen
Scaling High-Level Synthesis for Complex Image and Video Processing Designs

Some interesting papers from ESWeek 2011

Resource-aware Programming on Tiled Architectures
Symbolic Design Space Exploration for Multi-Mode Reconfigurable Systems
Capacity Metric for Chip Heterogeneous Multiprocessors

A Hybrid Strategy for Mapping Multiple Throughput-constrained Applications on MPSoCs  by Amit Kumar Singh, Akash Kumar and Thambipillai Srikanthan 
Analysis and Optimization of Fault-Tolerant Task Scheduling on Multiprocessor Embedded Systems 

List of high level synthesis tools

A good listing of high level synthesis tools.
http://stackoverflow.com/questions/5603285/c-to-hardware-compiler-hll-synthesis

Hello World :)