pips
icd
rose
cloog
CETUS
OSCAR
Friday, September 21, 2012
Thursday, September 20, 2012
Thursday, September 6, 2012
Wednesday, September 5, 2012
list of fpl 2012
Convey Vector Personalities – FPGA Acceleration with an OpenMP-Like Programming Effort?
Björn Meyer, Jörn Schumacher, Christian Plessl and Jens Förstner
PolyBlaze: From One to Many. Bringing the Microblaze Into the Multicore Era with Linux SMP Support
Eric Matthews, Lesley Shannon and Alexandra Fedorova
Automating the Design of MLUT MPSoPC FPGAs in the Cloud
David Andrews, Miaoqing Huang, Azad Fakhari, Eugene Cartwright, Sen Ma, Christina Smith and Jason Agron
Reconfigurable Multi-Processor Architecture For Streaming Applications
Leyla S. Ghazanfari, Roberto Airoldi, Jari Nurmi and Tapani Ahonen
High Level Structural Description of Streaming Applications
Anja Niedermeier, Jan Kuper and Gerard J.M. Smit
Combining Data and Computation Transformations for Fine-Grain Reconfigurable Architectures
Cristiano B. Oliveira and Eduardo Marques
Raising the Abstraction Level of HDL for Control-Dominant Applications
Marc-Andre Daigneault and Jean Pierre David
From OpenCL to High-Performance Hardware on FPGAs
Tomasz S. Czajkowski, Utku Aydonat, Dmitry Denisenko, John Freeman, Michael Kinsner, David Neto, Jason Wong, Peter Yiannacouras and Deshanand P. Singh
PPMC : Hardware Scheduling and Memory Management Support for Multi Accelerators
Tassadaq Hussain, Miquel Pericàs, Nacho Navarro and Eduard Ayguadé
DWARV 2.0: A CoSy-based C-to-VHDL Hardware Compiler
Razvan Nane, Vlad-Mihai Sima, Bryan Olivier, Roel Meeuws, Yana Yankova and Koen Bertels
Design Space Exploration for Automatically Generated Cryptographic Hardware Using Functional Languages
Davy Wolfs , Kris Aerts and Nele Mentens
Björn Meyer, Jörn Schumacher, Christian Plessl and Jens Förstner
PolyBlaze: From One to Many. Bringing the Microblaze Into the Multicore Era with Linux SMP Support
Eric Matthews, Lesley Shannon and Alexandra Fedorova
Automating the Design of MLUT MPSoPC FPGAs in the Cloud
David Andrews, Miaoqing Huang, Azad Fakhari, Eugene Cartwright, Sen Ma, Christina Smith and Jason Agron
Reconfigurable Multi-Processor Architecture For Streaming Applications
Leyla S. Ghazanfari, Roberto Airoldi, Jari Nurmi and Tapani Ahonen
High Level Structural Description of Streaming Applications
Anja Niedermeier, Jan Kuper and Gerard J.M. Smit
Combining Data and Computation Transformations for Fine-Grain Reconfigurable Architectures
Cristiano B. Oliveira and Eduardo Marques
Raising the Abstraction Level of HDL for Control-Dominant Applications
Marc-Andre Daigneault and Jean Pierre David
From OpenCL to High-Performance Hardware on FPGAs
Tomasz S. Czajkowski, Utku Aydonat, Dmitry Denisenko, John Freeman, Michael Kinsner, David Neto, Jason Wong, Peter Yiannacouras and Deshanand P. Singh
PPMC : Hardware Scheduling and Memory Management Support for Multi Accelerators
Tassadaq Hussain, Miquel Pericàs, Nacho Navarro and Eduard Ayguadé
DWARV 2.0: A CoSy-based C-to-VHDL Hardware Compiler
Razvan Nane, Vlad-Mihai Sima, Bryan Olivier, Roel Meeuws, Yana Yankova and Koen Bertels
Design Space Exploration for Automatically Generated Cryptographic Hardware Using Functional Languages
Davy Wolfs , Kris Aerts and Nele Mentens
Subscribe to:
Posts (Atom)