Updated Sobel Filter on zedboard

Previously I posted a reference design for the zedboard here.  http://shakithweblog.blogspot.de/2012/12/getting-sobel-filter-application.html

A newer version that reduced the communication bottleneck is posted here.
http://parse.ele.tue.nl/research/usbcam/

High Level Synthesis: Where Are We? A Case Study on Matrix Multiplication

http://samskalicky.files.wordpress.com/2013/10/ieee-pdf-express-plus-checked-version1.pdf

Related Work for MAMPSx

The HeartBeat model: a platform abstraction
enabling fast prototyping of real-time applications on
NoC-based MPSoC on FPGA
http://www.mes.tu-darmstadt.de/media/mikroelektronische_systeme/pdf_3/recosoc2013/slides_1/session5_1/1_Robino.pdf
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6581536&sortType%3Dasc_p_Sequence%26filter%3DAND(p_IS_Number%3A6581516)

To Read - On an external memory scheme for processor arrays for HLS

https://www.jstage.jst.go.jp/article/elex/10/14/10_10.20130324/_pdf

Energy and Performance Exploration of Accelerator Coherency Port Using Xilinx ZYNQ

http://www.googoolia.com/downloads/papers/sadri_fpgaworld_ver2.pdf

Xilinx going towards OpenCL

http://www.xilinx.com/products/design-tools/all-programmable-abstractions.html

Dataflow based HLS - Synflow Studio

https://www.synflow.com/

High Level Synthesis Design Contest

http://jcraconf.org/contest/index.html

Face Detection Videos

http://www.youtube.com/watch?v=sWTvK72-SPU
http://www.youtube.com/watch?v=WfdYYNamHZ8

to read

A Survey of High Level Synthesis Languages, Tools, and Compilers for Reconfigurable High Performance Computing

http://www2.cose.isu.edu/~zydedawi/Research/publications.php

Programming Model from the IBM SyNAPSE Chips

http://www-03.ibm.com/press/us/en/pressrelease/41710.wss

to read from Electronic System Level Synthesis Conference

http://www.ecsi.org/eslsyn2013/proceedings
System level synthesis of dataflow programs: HEVC decoder case study

How to Get My Paper Accepted at Top Software Engineering Conferences

http://www.slideshare.net/alexorso/how-to-get-my-paper-accepted-at-top-software-engineering-conferences

Slides from dutch bitchips hardware conference is out

http://www.hardwareconference.nl/programma/programma-2013.html

Selected titles:
Kester Aernoudt, Xilinx
Enabling new product innovations across markets with Zynq-7000 all-programmable SoC and Vivado HLS

Dirk van den Heuvel, Topic
Designing with heterogeneous multicore systems-on-chip in medical applications

Interesting DAC 2013 Papers

• Memory partitioning for multidimensional arrays in high-level synthesis
• The ITRS design technology and system drivers roadmap: process and status
• Runtime dependency analysis for loop pipelining in high-level synthesis
• On learning-based methods for design-space exploration with high-level synthesis
• 
  

Related Work for DSE in HLS

On Learning-Based Methods for Design-Space Exploration
with High-Level Synthesis

http://delivery.acm.org/10.1145/2490000/2488795/a50-liu.pdf?ip=131.155.41.196&acc=ACTIVE%20SERVICE&key=C2716FEBFA981EF12214637723A2BFB946E5CCD26CF057B5&CFID=222938095&CFTOKEN=27113601&__acm__=1370512562_6472454faaf574797c50528a567d9ac9

The San Diego Vision Benchmark Suite

The San Diego Vision Benchmark Suite

Useful benchmark suite!

Differences between AXI Streaming and FSL

According to the UG761 AXI Reference Guide, the mapping of FSL Signals to AXI Streaming Signals is as follows:

But in actual fact, M_AXIS_TREADY = ! FSL_M_FULL, since it's active high. The rest of the signals has a direct one to one mapping.

Also there is slight handshaking difference.
The AXI_M_TVALID signal cannot be deasserted after being asserted unless a transfer is
completed with AXI_TREADY. However, a AXI_TREADY can be asserted and deasserted
whenever the AXI4-Stream slave requires assertion and deassertion.

A master is not permitted to wait until TREADY is asserted before asserting TVALID. Once
TVALID is asserted it must remain asserted until the handshake occurs.

That means what in FSL
 if (!M_FULL)
   M_Write

looks like this in AXI Streaming Masters.
M_Write
wait until !M_FULL

References:
AMBA 4 AXI4-Stream Protocol Specification
UG761 AXI Reference Guide