According to the UG761 AXI Reference Guide, the mapping of FSL Signals to AXI Streaming Signals is as follows:
But in actual fact, M_AXIS_TREADY = ! FSL_M_FULL, since it's active high. The rest of the signals has a direct one to one mapping.
Also there is slight handshaking difference.
The AXI_M_TVALID signal cannot be deasserted after being asserted unless a transfer is
completed with AXI_TREADY. However, a AXI_TREADY can be asserted and deasserted
whenever the AXI4-Stream slave requires assertion and deassertion.
A master is not permitted to wait until TREADY is asserted before asserting TVALID. Once
TVALID is asserted it must remain asserted until the handshake occurs.
That means what in FSL
if (!M_FULL)
M_Write
looks like this in AXI Streaming Masters.
M_Write
wait until !M_FULL
References:
AMBA 4 AXI4-Stream Protocol Specification
UG761 AXI Reference Guide
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