DAC 2012 papers

1. Optimizing Memory Hierarchy Allocation with Loop Transformations for High-Level Synthesis
Jason Cong, Peng Zhang, Yi Zou

2. An Efficient Design Approach of Control Logic with the Use of High Level Synthesis for a Video Signal Conversion FPGA Ryo Yamamoto - Mitsubishi Electric Corp., Kamakura, Japan

3.Exploring AES Design Variants with C-to- Gates for FPGA at Gb/s Line Rates Kees Vissers, Fernando Martinez Vallina, Stephen Neuendorffer - Xilinx, Inc., San Jose, CA
Kristof Denolf, Ronny Dewaele - Barco, Kortrijk, Belgium

4. A Methodology for the High-Level Synthesis of Iterative Algorithms Alessandro A. Nacci, Francesco Bruschi, Vincenzo Rana - Politecnico di Milano, Italy

5. Hardware Synthesis of Recursive Functions through Partial Stream Rewriting
Lars Middendorf, Christian Haubelt - Univ. of Rostock, Rostock-Warnemuende, Germany
Christophe Bobda - Univ. of Arkansas, Fayetteville, AR

6. Accelerating Neuromorphic Vision Algorithms for Recognition Vijaykrishnan Narayanan, Ahmed Al Maashri, Michael Debole, Matthew Cotter, Nandhini Chandramoorthy,Yang Xiao - Pennsylvania State Univ., University Park, PA
Chaitali Chakrabarti - Arizona State Univ., Phoenix, AZ

7. A Compiler and Runtime for Heterogeneous Computing Rodric Rabbah, Joshua Auerbach, David F. Bacon, Ioana Burcea, Perry Cheng, Stephen J. Fink, Sunil Shukla -
IBM T.J. Watson Research Ctr., Yorktown Heights, NY

8. Removing Overhead from High-Level Interfaces
Kyle Kelley, Megan Wachs, John P. Stevenson,
Stephen Richardson, Mark Horowitz - Stanford Univ., Stanford, CA

9. Communication-Aware Mapping of KPN Applications onto Heterogeneous MPSoCs
Jeronimo Castrillon, Andreas Tretter, Rainer Leupers,
Gerd Ascheid - RWTH Aachen Univ., Aachen, Germany

10. Unrolling and Retiming of Stream Applications onto Embedded Multicore Processors
Weijia Che, Karam S. Chatha - Arizona State Univ., Tempe, AZ